SHANGHAI -- eriSilicon (688521.SH) released the ZSP5000 Digital Signal Processing (DSP) series IPs, which are based on its fifth-generation silicon-proven DSP architecture. This product line adopts a highly scalable and energy-efficient design, and has been deeply optimized for compute-intensive workloads such as computer vision and embedded AI. Combined with the configurable nature of the architecture, this series of IP can provide excellent solutions with both energy and computing efficiency for various edge devices.

The ZSP5000 series IPs include ZSP5000, ZSP5000UL, ZSP5000L, and ZSP5000H, delivering scalable vector processing performance ranging from 32 to 256 8-bit Multiply-Accumulate (MAC) operations per cycle. For even higher performance, VeriSilicon’s multi-core ZSP5400H can combine multiple ZSP5000H cores in a multi-cluster architecture to further scale computing capability.

The ZSP5000 series features a rich and intuitive instruction set optimized for ease of programming and efficient performance tuning, while its dedicated instructions accelerate common imaging and signal processing tasks such as vector-scalar arithmetic, horizontal reductions, permutations, shifts, table lookups, clamping, and averaging. It integrates the ZTurbo coprocessor interface, allowing customers to easily add custom instructions and hardware accelerators within the same pipeline, and is compatible with the OpenCV Application Programming Interface (API), ensuring seamless integration with the mainstream computer vision frameworks. Additionally, the ZSP5000 series is equipped with a full-featured memory subsystem, a multi-channel 3D DMA engine, and a scalable multicore configuration, supporting flexible deployment for a broad spectrum of applications.

The ZSP5000 series IPs are backward compatible with VeriSilicon’s scalar ZSPNano series, efficiently handling mixed MCU and DSP workloads. VeriSilicon also offers comprehensive ZView development tools, including an Eclipse-based Integrated Development Environment (IDE), cycle-accurate simulator, optimizing compiler, debugger, and profiling tools, streamlining software development and system integration.

“With the growing adoption of OpenCV and the increasing demand for computer vision workloads alongside NPUs in edge intelligence computing, we are introducing the ZSP5000—our next-generation DSP IP series. It supports the industry-standard OpenCV API, enables streamlined interfacing with NPUs via our FLEXA interface, and integrates built-in audio processing capabilities for multi-modal applications,” said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Division at VeriSilicon. “Energy efficiency is key at the edge, and the ZSP5000 series IPs feature an optimized memory access architecture to minimize processor power consumption. It also features ZTurbo, a custom instruction extension mechanism designed for targeted applications, which enables further power and performance optimization through seamless integration of hardware accelerators. Our leading customers are already leveraging these capabilities to achieve significant advancements in power and performance.”